1. Field of the Invention
The present invention generally relates to data transfer via PCI-X (Peripheral Component Interconnect-X) bridges, and more particularly to data transfer via Host/PCI-X bridges.
2. Description of the Related Art
In a conventional computer system, a Host/PCI-X bridge couples a Front Side Bus (FSB) and a PCI-X Bus (called PCI-X Bus 0). There may be a PCI-X device coupled to the PCI-X Bus 0. The FSB is connected to at least a processor and main memory. The processor, the main memory, and the PCI-X device communicate with each other via the FSB, the Host/PCI-X bridge, and the PCI-X Bus 0.
In such a conventional system, the processor stalls periodically during this time the processor is idle and unavailable to perform other tasks.
By way of installation, assume the processor needs to execute a read instruction reading data from the PCI-X device to the processor. The processor sends a read command and the address of the PCI-X device to the Host/PCI-X bridge via the FSB. Then, the processor stalls waiting for the requested data from the Host/PCI-X bridge. In response, the Host/PCI-X bridge forwards the read command and the address of the PCI-X device to the PCI-X device via the PCI-X Bus 0. Then, the PCI-X device gathers and sends the requested data back to the Host/PCI-X bridge via the PCI-X Bus 0. Finally, the Host/PCI-X bridge forwards the requested data to the processor via the FSB. After receiving the requested data from the Host/PCI-X bridge, the processor executes the next instruction.
Assume the processor later needs to execute a write instruction writing data from the processor to the PCI-X device. The processor sends a write command, the write data, and the address of the PCI-X device to the Host/PCI-X bridge via the FSB. Then, the processor stalls waiting for the write data to be written to the PCI-X device. In response, the Host/PCI-X bridge forwards the write command, the write data, and the address of the PCI-X device to the PCI-X device via the PCI-X Bus 0. After receiving the write data, the PCI-X device sends a write completion signal to the Host/PCI-X bridge via the PCI-X bus 0. Finally, the Host/PCI-X bridge forwards the write completion signal to the processor via the FSB. After receiving the write completion signal from the Host/PCI-X bridge, the processor executes the next instruction.
In summary, the execution of the read instruction causes the processor to stall until the requested data is returned. Similarly, the execution of the write instruction also causes the processor to stall until the write data is written to the PCI-X device. However, processor stalling deteriorates processor performance and, as such, is undesirable.
One prior art solution requires another processor to handle read or write instructions for the main processor. However, using an additional processor is costly and wastes precious real estate.
Accordingly, there is a need for an apparatus and method in which reading from and writing to a PCI-X device via a bridge are performed without processor stalling and without the use of an additional processor.